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Microchip dsPIC33FJ128MC802 (DIP) (LIQ)

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Descripción

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Operating Range:

    • Up to 40 MIPS operation (at 3.0-3.6V):
    • Industrial temperature range (-40°C to +85°C)
    • Extended temperature range (-40°C to +125°C)
    • Hight temperature range (-40°C to +150°C)

High-Performance DSC CPU:

  • Modified Harvard architecture
  • C compiler optimized instruction set
  • 16-bit wide data path
  • 24-bit wide instructions
  • Linear program memory addressing up to 4M instruction words
  • Linear data memory addressing up to 128 Kbytes
  • 83 base instructions: mostly 1 word/1 cycle
  • Two 40-bit accumulators with rounding and saturation options
  • Flexible and powerful addressing modes:
    • Indirect
    • Modulo
    • Bit-Reversed
  • Software stack
  • 16 x 16 fractional/integer multiply operations
  • 32/16 and 16/16 divide operations
  • Single-cycle multiply and accumulate:
    • Accumulator write back for DSP operations
    • Dual data fetch
  • Up to ±16-bit shifts for up to 40-bit data

On-Chip Flash and SRAM:

  • Flash program memory
  • Data SRAM
  • Boot, Secure, and General Security for program Flash

Direct Memory Access (DMA):

  • 8-channel hardware DMA
  • Up to 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA:
    • Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
  • Most peripherals support DMA

Timers/Capture/Compare/PWM:

  • Timer/Counters, up to five 16-bit timers:
    • Can pair up to make two 32-bit timers
    • One timer runs as a Real-Time Clock with an external 32.768 kHz oscillator
    • Programmable prescaler
  • Input Capture (up to four channels):
    • Capture on up, down or both edges
    • 16-bit capture input functions
    • 4-deep FIFO on each capture
  • Output Compare (up to four channels):
    • Single or Dual 16-bit Compare mode
    • 16-bit Glitchless PWM mode
  • Hardware Real-Time Clock/Calendar (RTCC):
    • Provides clock, calendar, and alarm functions

Interrupt Controller:

  • 5-cycle latency
  • 118 interrupt vectors
  • Up to 53 available interrupt sources
  • Up to three external interrupts
  • Seven programmable priority levels
  • Five processor exceptions

Digital I/O:

  • Peripheral pin Select functionality
  • Up to 35 programmable digital I/O pins
  • Wake-up/Interrupt-on-Change for up to 21 pins
  • Output pins can drive from 3.0V to 3.6V
  • Up to 5V output with open drain configuration
  • All digital input pins are 5V tolerant
  • 4 mA sink on all I/O pins

System Management:

  • Flexible clock options:
    • External, crystal, resonator, internal RC
    • Fully integrated Phase-Locked Loop (PLL)
    • Extremely low jitter PLL
  • Power-up Timer
  • Oscillator Start-up Timer/Stabilizer
  • Watchdog Timer with its own RC oscillator
  • Fail-Safe Clock Monitor
  • Reset by multiple sources

Power Management:

  • On-chip 2.5V voltage regulator
  • Switch between clock sources in real time
  • Idle, Sleep, and Doze modes with fast wake-up

Analog-to-Digital Converters (ADCs):

  • 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
    • Two and four simultaneous samples (10-bit ADC)
    • Up to nine input channels with auto-scanning
    • Conversion start can be manual or synchronized with one of four trigger sources
    • Conversion possible in Sleep mode
    • ±2 LSb max integral nonlinearity
    • ±1 LSb max differential nonlinearity

Comparator Module:

  • Two analog comparators with programmable input/output configuration

CMOS Flash Technology:

  • Low-power, high-speed Flash technology
  • Fully static design
  • 3.3V (±10%) operating voltage
  • Industrial and Extended temperature
  • Low power consumption

Motor Control Peripherals:

  • 6-channel 16-bit Motor Control PWM:
    • Three duty cycle generators
    • Independent or Complementary mode
    • Programmable dead time and output polarity
    • Edge-aligned or center-aligned
    • Manual output override control
    • One Fault input
    • Trigger for ADC conversions
    • PWM frequency for 16-bit resolution (@ 40 MIPS) = 1220 Hz for Edge-Aligned mode, 610 Hz for Center-Aligned mode
    • PWM frequency for 11-bit resolution (@ 40 MIPS) = 39.1 kHz for Edge-Aligned mode, 19.55 kHz for Center-Aligned mode
  • 2-channel 16-bit Motor Control PWM:
    • One duty cycle generator
    • Independent or Complementary mode
    • Programmable dead time and output polarity
    • Edge-aligned or center-aligned
    • Manual output override control
    • One Fault input
    • Trigger for ADC conversions
    • PWM frequency for 16-bit resolution (@ 40 MIPS) = 1220 Hz for Edge-Aligned mode, 610 Hz for Center-Aligned mode
    • PWM frequency for 11-bit resolution (@ 40 MIPS) = 39.1 kHz for Edge-Aligned mode, 19.55 kHz for Center-Aligned mode
  • 2-Quadrature Encoder Interface module:
    • Phase A, Phase B, and index pulse input
    • 16-bit up/down position counter
    • Count direction status
    • Position Measurement (x2 and x4) mode
    • Programmable digital noise filters on inputs
    • Alternate 16-bit Timer/Counter mode
    • Interrupt on position counter rollover/underflow

Communication Modules:

  • 4-wire SPI (up to two modules):
    • Framing supports I/O interface to simple codecs
    • Supports 8-bit and 16-bit data
    • Supports all serial clock formats and sampling modes
  • I2C™ :
    • Full Multi-Master Slave mode support
    • 7-bit and 10-bit addressing
    • Bus collision detection and arbitration
    • Integrated signal conditioning
    • Slave address masking
  • UART (up to two modules):
    • Interrupt on address bit detect
    • Interrupt on UART error
    • Wake-up on Start bit from Sleep mode
    • 4-character TX and RX FIFO buffers
    • LIN bus support
    • IrDA® encoding and decoding in hardware
    • High-Speed Baud mode
    • Hardware Flow Control with CTS and RTS
  • Enhanced CAN (ECAN. module) 2.0B active:
    • Up to eight transmit and up to 32 receive buffers
    • 16 receive filters and three masks
    • Loopback, Listen Only and Listen All
    • Messages modes for diagnostics and bus monitoring
    • Wake-up on CAN message
    • Automatic processing of Remote Transmission Requests
    • FIFO mode using DMA
    • DeviceNet. addressing support
  • Parallel Master Slave Port (PMP/EPSP):
    • Supports 8-bit or 16-bit data
    • Supports 16 address lines
  • Programmable Cyclic Redundancy Check (CRC):
    • Programmable bit